(A) Field of the Invention
The present invention is related to a method for forming a dielectric layer in a non-volatile memory device, more specifically, to a formation method of an oxide-nitride-oxide (ONO) layer.
(B) Description of the Related Art
Non-volatile memory devices are currently in wide use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the transistor. The electron transfer is initiated by either hot electron injection or Fowler-Nordheim tunneling. One important dielectric material for the fabrication of the floating-gate electrode is an ONO structure. During programming, electrical charges are transferred from the substrate to the silicon nitride layer in the ONO structure and trapped therein. Nowadays, the ONO structure is in wide use in non-volatile memory devices.
The ONO formation described in U.S. Pat. No. 5,168,334 is shown in FIG. 1, which is most commonly used. A bottom oxide layer 102 is thermally grown over the surface of a silicon substrate 101, and then an overlying layer 103 of silicon nitride is deposited to a thickness of around 200 angstroms. Next, a top oxide layer 104 is deposited on the silicon nitride layer 103, thereby an ONO layer 10 is formed.
U.S. Pat. Nos. 5,966,603 and 6,297,096 reveal another way of ONO formation. As shown in FIG. 2(a), a bottom oxide layer 202 is thermally grown on a silicon substrate 201, followed by depositing a silicon nitride layer 203. As shown in FIG. 2(b), an oxidation process is conducted to consume a part of the silicon nitride layer 203 into a top oxide layer 204, thereby an ONO layer 20 including the bottom oxide layer 202, the nitride layer 203 and the top oxide layer 204 is formed. It is noted that typically half of the thickness of the top oxide layer 204 comes from the consumed nitride layer 203. Thus, for instance, if it is desired to have a top oxide layer 204 of a thickness with around 100 angstroms, the silicon nitride layer 203 should be at least 50 angstroms thicker than the final desired nitride thickness, with the extra nitride being for consumption of the top oxide layer 204.
However, the top oxide layer 104 formed by deposition may incur oxide quality issue that is harmful to isolation, and the method that the top oxide layer 204 formed by oxidation may be not be able to easily control the thickness of the nitride layer 203. Therefore, it is necessary to develop other ONO formation methods for resolving the above-mentioned problems.